PN7462AU - MRA3

EEPROM Range:0x201200 - 0x201FFF

Total Structures:33

Page I [ErrorMem]

Starting Address : 0x201200

	Address	Type	Field Name	Default Value	Description
[Struct:1] Err 0x201200	Error information during ROM APIs
	0x201200	u8[36]	str_name	IntentionallyEmpty (cstring)	Reserved for MRA2 and MRA3
	0x201224	u32	dwCauseCode	0x00 (hex)	Error information from ROM Boot

Page II [Ctrl]

Starting Address : 0x201240

	Address	Type	Field Name	Default Value	Description
[Struct:1] VerInfo 0x201240	Version Information of the Layout Version 28.0.0: artf178091: [CR][FW][TXOCP] Load dependent RX gain control Version 27.0.0: artf203315 : The Default TVDD source config to be External. DPC 5V by default. Version 27.0.0: Clif EEPROM 1.9.2v Settings. Version 26.0.0: artf157683 : Changing the wWaitTime of Tx Ldo Params. [15:14] : Lfo Clock Value and [13:0] : Waiting Time after TxLdo is started. Version 25.5.0: artf156243 : Update according to the Analysis Information. Version 25.4.0: wWaitTime value for Tx Ldo start ir changed from 250us to 1100us. Version 25.3.0: dwTidtTimeAdjust field added. Version 25.2.0: RRDD value changed from 28us to 50us and dwExtRfOnTime values to 302us. Version 25.1.0: Adding the RRDD and Fdt values for Jewel. Version 25.0.0: Clif EEPROM 1.9v settings Version 24.0.2: [RC4] CLIF_ANA_NFCLD_REG.CM_RFL_NFC set to 7. [MRA3] v1.8.3 of EEPROM Version 24.0.1: Refactored dwFelicaRxRMSigproTime Version 24.0.0: Removed the Rf On and Off De-bouncing structure. : Added Rf Inter-Op timings structure and Rf hal timings : for different algos. Version 23.9.0: CLIF_ANA_NFCLD_REG.CM_RFL_NFC value changed from 7 to 3 Version 23.8.0: [MRA2] v1.8 of EEPROM Version 23.7.0: [MRA2] v1.7.4 of EEPROM Version 23.6.0: [MRA2] ClkGenClifClockStart->ClkModeAlmCm set to 0x50
	0x201240	u16	major	28 (int)	Major Version
	0x201242	u8	minor	0 (int)	Minor Version
	0x201243	u8	development	0 (int)	Development Version
	0x201244	u8[32]	str_name	Rf#v1.9 (cstring)	Canonical name to identify the EE Layout

Page III [Boot]

Starting Address : 0x201280

	Address	Type	Field Name	Default Value	Description
[Struct:1] RNG 0x201280	Random Number Generator. \see phhalRng_Init
	0x201280	u8	bTrngFeedTimeout	0x26 (hex)	Programmable wait time to release gated clocks feeding the TRNG

	Address	Type	Field Name	Default Value	Description
[Struct:2] ClkGen 0x201284	Clock Generator. \ref phhalClkGen_Init
	0x201284	u16	wXtalActivationTimeOut	2000 (int)	dwXtalActivationTimeOut Activation time out value
	0x201286	u8	eSource	0x00 (hex)	eSource Clock source selection, \see phhalClkGen_Source_t
	0x201287	u8	bKickOnError	0x00 (hex)	bKickOnError Kick on error.

	Address	Type	Field Name	Default Value	Description
[Struct:3] PcrPwrTempConfig 0x201288	Power Clock Reset Temperature Configuration related to \see phhalPcr_PwrTempConfig_t \warning This structure is tightly linked to \ref phhalPcr_PwrTempConfig_t
	0x201288	u8	bUseTempSensor0	0 (int)	Flag to indicate to use temperature sensor 0 or not 0 : Disabled 1 : Enabled
	0x201289	u8	bUseTempSensor1	0 (int)	Flag to indicate to use temperature sensor 1 or not 0 : Disabled 1 : Enabled
	0x20128a	u8	bLowTempTarget0	3 (int)	0 : 135 1 : 130 2 : 125 3 : 120
	0x20128b	u8	bLowTempTarget1	3 (int)	0 : 135 1 : 130 2 : 125 3 : 120
	0x20128c	u8	bHighTempTarget0	0 (int)	0 : 135 1 : 130 2 : 125 3 : 120
	0x20128d	u8	bHighTempTarget1	0 (int)	0 : 135 1 : 130 2 : 125 3 : 120

	Address	Type	Field Name	Default Value	Description
[Struct:4] PcrPwrDown 0x201290	See \ref phhalPcr_PwrDown_Setting_t It is a 32 bit value bit-file created by ORing enums of type \ref phhalPcr_PwrDown_Setting_t used to select which settings must be applied to reduce power consumption during Suspend
	0x201290	u32	dwPwrDownSettings	0x7FFFFFFF (hex)	0x7FFFFFFF : E_APPLY_ALL_SETTNGS. i.e. all power reduction settings will be applied during Suspend

	Address	Type	Field Name	Default Value	Description
[Struct:5] TxAnaStandByConfig 0x201294	TxAna register settings for standby \see phhalPcr_TxAnaStandByConfig_t
	0x201294	u32	dwAnaTxStandByValue	0F (hex)	To hold CLIF standby GSN value selection
	0x201298	u32	dwAnaTxProtStandByValue	03 (hex)	To hold the CLIF configuration related to powerdown

	Address	Type	Field Name	Default Value	Description
[Struct:6] EEPROM 0x20129c	EEPROM Access Settings. \see phhalEeprom_Init
	0x20129c	u8	bEnableFastMode	0 (int)	Disable Fast mode for EEPROM access 0 : Disabled 1 : Enabled

	Address	Type	Field Name	Default Value	Description
[Struct:7] FLASH 0x2012a0	Flash Settings. \see phhalFlash_Init
	0x2012a0	u8	bEnableFastMode	0 (int)	Enable or Disable fast mode for Page Flash access 0 : Disabled 1 : Enabled
	0x2012a1	u8	bEnableSkipProgramOnEraseFail	1 (int)	Setting to decide if program phase will be attempted in the event of an erase phase failure 0 : Program phase will be attempted even if erase phase failed 1 : Program phase will be skipped if erase phase failed

	Address	Type	Field Name	Default Value	Description
[Struct:8] TxLdoParams 0x2012a4	Power management unit. \see phhalPmu_TxLdoInit and \see phhalPmu_TxLdoParams_t
	0x2012a4	u8	bUseTxLdo	0x00 (hex)	Parameter to use internal TxLDO or external TxLDO for TVDD Source 0 : Use external TxLDO 1 : Use internal TxLDO
	0x2012a5	u8	eFullPowerTvddSel	0x04 (hex)	TVDD Power Selection for Reader Mode. \see phhalPmu_TvddSel_t 0 : 3V 1 : 3.3V 2 : 3.6v 3 : 4.5V 4 : 4.7v other : Invalid
	0x2012a6	u8	eLowPowerTvddSrc	0x00 (hex)	Source for the TVDD \see phhalPmu_LowPower_TvddSrc_t 0 : Source is TVDD In 1 : Source is VUP 2 : Source is VBUS other : Invalid
	0x2012a7	u8	bOverCurrentEnable	0x00 (hex)	Over Current Interrupt Enable or disable 0 : Disabled Others : Enable
	0x2012a8	u16	wWaitTime	50272 (int)	[15:14] : Lfo Clock Value and [13:0] : Waiting Time after TxLdo is started. Lfo Clk = 3 and Waiting Time = 1120us.

	Address	Type	Field Name	Default Value	Description
[Struct:9] CT 0x2012ac	Initial settings for CT Interface. \see phhalCt_InitParam_t
	0x2012ac	u8	bPullUp	1 (hex)	Pull UP Configuration 0 : Pull Down 1 : Pull UP others : Undefined behaviour
	0x2012ad	u8	bConnectorType	1 (hex)	Connector Type 0 : Normally Closed others : Normally Open
	0x2012ae	u8	bAutoCTDeactivationEnable	1 (hex)	Auto deactivation 0 : Disabled others : Enabled
	0x2012af	u8	bSlewRate	0x38 (hex)	CLK,IO,VCC slew rate 0 : CLK,IO,VCC slew rate others : This value is directly mapped to ct_srr_reg to give enough options

	Address	Type	Field Name	Default Value	Description
[Struct:10] GPIO 0x2012b0	GPIO Bootup Configuration. Each byte represents a Gpio configuration starting from Gpio 1 to 12.
	0x2012b0	u8[12]	OutputPUPD	00 00 00 00 00 00 03 03 07 03 03 03 (hex)	Lower Nibble - Related to output configuration Upper Nibble - Related to Pull-up/Pull-down configuration Bit0=0 : Skip Configuration as output on Boot Bit0=1 : Configure Gpio as output Bit1=1 : Enable slew-rate Bit2=1 : Drive the output high Bit2=0 : Drive the output low Bit5=1 : Apply Pull UP Bit6=1 : Apply Pull Down
	0x2012bc	u8[12]	InputISR	00 00 00 00 00 00 00 00 00 00 00 00 (hex)	ALL=0 : Skip Configuration on Boot Bit0=0 : Un-Configure as input Bit0=1 : Configure/SET as Input Bit1=1 : GPIO is a wakeup source Bit2=1 : GPIO is an interrupt source Bit4=1 : Level Sensitive Interrupt Bit5=1 : Interrupt on Active Low or Falling Edge Bit6=1 : Interrupt on Both Edges

Page IV [HW]

Starting Address : 0x201300

	Address	Type	Field Name	Default Value	Description
[Struct:1] WakeUpConfig 0x201300	Wakeup Sources \see phhalPcr_WakeUpConfig_t
	0x201300	u16	wWakeUpTimerVal	300 (int)	Timer value for the wake up in milliseconds
	0x201302	u8	bEnableHIFWakeup	0 (int)	Flag to know the host interface wake up 0 : Disabled 1 : Enabled
	0x201303	u8	bI2CAddr	0x28 (hex)	I2C address if the wake up is configured for HIF
	0x201304	u8	bWakeUpTimer	1 (int)	Flag to enable the wake up timer as wake up source 0 : Disabled 1 : Enabled
	0x201305	u8	bWakeUpRfLdt	0 (int)	Flag to enable the RfLdt as wake up source 0 : Disabled 1 : Enabled
	0x201306	u8	bWakeUpPvddLim	1 (int)	Flag to enable Pvdd current limitation as wake up source when it goes below the lower threshold 0 : Disabled 1 : Enabled
	0x201307	u8	bWakeUpCtPr	1 (int)	Flag to enable CT presence as wake up source when it goes below the lower threshold 0 : Disabled 1 : Enabled
	0x201308	u8	bWakeUpIntAux	0 (int)	Flag to enable PVDD Auxiliary interrupt as wake up source when it goes below the lower threshold 0 : Disabled 1 : Enabled
	0x201309	u8	bWakeUpTvddMon	0 (int)	Flag to enable Tvdd Monitoring as wake up source when it goes below the lower threshold 0 : Disabled 1 : Enabled
	0x20130a	u8	bWakeUpGpio	0 (int)	Flag to enable Gpio as wake up source when it goes below the lower threshold 0 : Disabled 1 : Enabled

	Address	Type	Field Name	Default Value	Description
[Struct:2] RfAntennae 0x20130c	Antennae type. ALM or PLM
	0x20130c	u8	enableALM	0 (hex)	1 : ALM is used. 0 : PLM is used.

	Address	Type	Field Name	Default Value	Description
[Struct:3] RfInitUserEE 0x201310	\see phhalRf_InitUserEE_t
	0x201310	u32	dwAgcConfig1CMValue	0x0107FF7 (hex)	Card mode AGC Config1 value
	0x201314	u32	dwAgcConfig0CMValue	0x44003 (hex)	Card mode AGC Config0 value
	0x201318	u32	dwLCPDRefValue	0x000020AC (hex)	Reference value of AGC for LPCD
	0x20131c	u32	dwLCPDThreashold	0x00000005 (hex)	Threshold value for LPCD
	0x201320	u32	dwLCPDDurations	0x00000028 (hex)	Duration value for LPCD
	0x201324	u16	wAgcCMInputValue	0x00 (hex)	Card Mode most possible sensitive input value
	0x201326	u8	bAnaNFCLD	0x0C (hex)	NFC LD Threshold value
	0x201327	u8	bAnaTxProt	0x09 (hex)	Initial value for Ana Tx Prot Register

	Address	Type	Field Name	Default Value	Description
[Struct:4] RfDPC 0x201328	\see phhalRf_DPCConfig_t
	0x201328	u16	wControlCycle	0x4E20 (hex)	Sets the value for the periodic regulation. Time base is 1/20Mhz. (Example: Value of 20000 is equal to 1ms)
	0x20132a	u16	wAgcFastModeConfig	0x2540 (hex)	Controls AGC FastMode (StepSizeEnabled: 13 + StepSize: 12..11 + DurationEnabled: 10 + Duration: 9..0 )
	0x20132c	u16	wAgcTrshLow	0x144 (hex)	Low threashold for gearshift
	0x20132e	u16	wGuardTimeFastMode	0x88B8 (hex)	Guard time after AGC fast mode has been triggered. This happens in the following scenarios: - End of Receive - End of Transmit - After a gear switch Time base is 1/20MHz (Example: Value of 2000 is equal to 100us)
	0x201330	u16	wGuardTimeSofDetected	0x61A8 (hex)	Guard time after SoF or SC detection. This is to avoid any DPC regulation between SoF/SC and actual begin of reception. Time base is 1/20MHz (Example: Value of 2000 is equal to 100us)
	0x201332	u16	wGuardTimeFieldOn	0x0190 (hex)	Guard time after Gear Switch during FieldOn instruction. Time base is 1/20MHz (Example: Value of 2000 is equal to 100us)
	0x201334	u16[15]	wAgcTrshHigh	0x014A 0x014B 0x014A 0x0148 0x0146 0x0143 0x013D 0x012E 0x0170 0x00AD 0x00A7 0x009E 0x0096 0x0087 0x004A (hex)	High threasholds for each gear
	0x201352	u8	bOcProtControl	0x73 (hex)	Control byte (StartGear: 7..4 bits + GearStep: 3..1 bits + OcProtLoopEnabled: 0 bit )
	0x201353	u8	bAgcXi	0x0 (hex)	Compensation value for the AGC
	0x201354	u8	bDebug	0x0 (hex)	Enable/Disable debug signals
	0x201355	u8	bAgcShiftValue	0x05 (hex)	Shift value for AGC dynamic low threshold adjustment
	0x201356	u8	bSizeOfLUT	0x09 (hex)	Number of fields in the following configuration look up table
	0x201357	u8[15]	bConfigLUT	0xF9 0xF1 0xF3 0xF5 0xF7 0xF0 0xF2 0xF4 0xF6 0x96 0x66 0x46 0x36 0x26 0x16 (hex)	Look up table for configuration values

	Address	Type	Field Name	Default Value	Description
[Struct:5] RfPcdShaping 0x201368	\see phhalRf_PcdShapeConfig_t
	0x201368	u32[20]	dwConfiguration	0x08079991 0x00089991 0x17A09991 0x0040F991 0x0010B992 0x00209BA2 0x0040E9A2 0x00089A92 0x0080F992 0x08479093 0x080799A7 0x00089997 0x17309997 0x00014681 0x00104A85 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 (hex)	The lookup table for the configuration for PCD shaping.
	0x2013b8	u8	bSizeOfLUT	0x2D (hex)	Number of elements in the following configuration look up table.

	Address	Type	Field Name	Default Value	Description
[Struct:6] RfAPC 0x2013bc	APC Settings
	0x2013bc	u16	bRssiTimer	0x423 (hex)	Periodic timer to reapply RSSI while transceiver is in Wait4Data state. Unit is 128/fc (106kHz) if set to 0 it means feature is not used 0423 == ~10ms
	0x2013be	u8	bRssiLutSize	0x10 (hex)	Size of LUT: DO NOT MODIFY this parameter
	0x2013bf	u8	bRssiNbEntries	0x00 (hex)	Number of entries in RSSI look up table (it refers to dwRssiEntry0 to dwRssiEntryX). If set to 0 then no RSSI algo is applied
	0x2013c0	u32[16]	dwRssiEntry	0x84000000 0x009806C0 0x00C41180 0x00D81E00 0x00DA2580 0x01202F80 0x00243700 0x00AA3E80 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 (hex)	Purpose of each bits: bits 26:24 = TXLDO output voltage: PMU_TXLDO_CONTROL_REG / TXLDO_SELECT bits 23:22 = CLIF_ANA_TX_AMPLITUDE_REG / TX_CW_AMPLITUDE_ALM_CM bits 21:21 = CLIF_TX_CONTROL_REG / TX_ALM_TYPE_SELECT bits 20:16 = CLIF_ANA_TX_AMPLITUDE_REG / TX_RESIDUAL_CARRIER bits 15:00 = CLIF_RSSI_REG / AGC_VALUE[15:6] + ADC_DATA_Q[5:0]
	0x201400	u32	dwRssiEntry0overwrite	0x03000000 (hex)	Replacement of dwRssiEntry[0] for trigger ReqA/ReqB

	Address	Type	Field Name	Default Value	Description
[Struct:7] RfInterOpTimings 0x201404	Rf Timings for the Inter-op issues
	0x201404	u32	dwExtRfOnTime	302 (int)	Value of Time(us) for Peer to turn the Rf On
	0x201408	u32	dwExtRfOffTime	10 (int)	Value of Time(us) for Peer to turn the Rf off after Transmitting data
	0x20140c	u32	dwIntRfOnTime	302 (int)	Value of Time(us) for Internal Rf On in active communication
	0x201410	u32	dwRRDDTime	50 (int)	Value of Time(us) for RRDD for Jewel (((28 + (2 * 9.44)) + Tolerence) = 50).
	0x201414	u32	dwTidtTimeAdjust	50 (int)	Value of Time(us) for Tidt adjust to meet the spec timings of Tadt(Tadt > 768/fc(~57)).

	Address	Type	Field Name	Default Value	Description
[Struct:8] RfHalTimings 0x201418	Rf Timings different algo.
	0x201418	u32	dwClkErrRecoveryTime	50 (int)	Time(us) for Clock Error Recovery
	0x20141c	u32	dwRfOffDeBouncingTime	20 (int)	Time(us) for External Rf off De-Bouncing
	0x201420	u32	dwPbfAlmFwResetTime	100 (int)	Time(us) for Pbf Alm Fw Reset Timer
	0x201424	u32	dwFelicaRxRMSigproTime	2000 (int)	Time(us) for Felica Stuck Timer in Card mode when SIGPRO RM is used

	Address	Type	Field Name	Default Value	Description
[Struct:9] DPLLCfg 0x201428	DPLL Configurations
	0x201428	u32	DpllControl	0x63 (hex)	Dpll Control
	0x20142c	u32	DpllInit	0x00171433 (hex)	Dpll Init
	0x201430	u32	DpllGear	0x00042A55 (hex)	Dpll Gear
	0x201434	u32	DpllInitFreq	0x80008591 (hex)	Dpll Init Freq

	Address	Type	Field Name	Default Value	Description
[Struct:10] DPLLClkPhaseAdjustment 0x201438	DPLL Clock Phase Adjustment Configuration
	0x201438	u32	DpllInitCeA	0x00000000 (hex)	Dpll Init value for card emulation A
	0x20143c	u32	AnaClkManCeA	0x00000005 (hex)	Value of Ana Clk Man for card emulation A
	0x201440	u32	DpllInitCeB	0x00000000 (hex)	Dpll Init value for card emulation B
	0x201444	u32	AnaClkManCeB	0x00000005 (hex)	Value of Ana Clk Man for card emulation B
	0x201448	u32	DpllInitCeF	0x00000000 (hex)	Dpll Init value for card emulation F
	0x20144c	u32	AnaClkManCeF	0x00000005 (hex)	Value of Ana Clk Man for card emulation F

	Address	Type	Field Name	Default Value	Description
[Struct:11] RfLdtParams 0x201450	\see phhalPcr_RfLdtParams_t
	0x201450	u8	bRfldRefLo	02 (int)	Higher Reference Value for RF Level Detector
	0x201451	u8	bRfldRefHi	03 (int)	Lower Reference Value for RF Level Detector
	0x201452	u8	bEnableAdvancedRFLD	0 (int)	Should we used advanced RFLD Feature or normal RFLD Feature
	0x201453	u8	bPadding	0 (int)	Structure padding.

	Address	Type	Field Name	Default Value	Description
[Struct:12] RfTestBus 0x201454	Test Bus configuration of RF
	0x201454	u32	dwAnaTB	0x00000000 (hex)	0x00: No Analog Test Bus Signal Enabled
	0x201458	u32	dwDAC	0x00000000 (hex)	0x00 : No Analog Test Bus Signal Enabled
	0x20145c	u8	bTbDigi1	0x02 (hex)	0x02 : Tx Active
	0x20145d	u8	bTbDigi2	0x00 (hex)	0x00 : No Digital Test Bus Signal2 Enabled

	Address	Type	Field Name	Default Value	Description
[Struct:13] ClkGenClifClockStart 0x201460	Configuration for ClkGen to start Clif Clock
	0x201460	u8	ClkModePassiveRm	0x00 (hex)	Value of Ana Clk field for Passive Reader Mode
	0x201461	u8	ClkModeActive	0x10 (hex)	Value of Ana Clk field for Active Mode
	0x201462	u8	ClkModePlmCm	0x50 (hex)	Value of Ana Clk field for PLM Card Mode
	0x201463	u8	ClkModeAlmCm	0x50 (hex)	Value of Ana Clk field for Alm Card Mode

	Address	Type	Field Name	Default Value	Description
[Struct:14] I2CM 0x201464	Default configuration for I2C Master. These values are primarily used for phExHif.
	0x201464	u32	dwDataRateHz	100000 (int)	I2C Master transaction data rate in Hz.
	0x201468	u8	bSlaveAddr	0x28 (hex)	I2C 7-bit slave address.

	Address	Type	Field Name	Default Value	Description
[Struct:15] SPIM 0x20146c	SPI Master configurations
	0x20146c	u8	bModes	00 (hex)	Specifies the SPIM mode (CPOL, CPHA) of operation, \see phhalSPIM_Modes_t.
	0x20146d	u8	bDataRate	00 (hex)	Specifies the SPIM transaction data rate. \see phhalSPIM_Configure 0 : 1.0 MHz 1 : 1.51 MHz 2 : 2.09 MHz 3 : 2.47 MHz 4 : 3.01 MHz 5 : 4.52 MHz 6 : 5.42 MHz 7 : 6.78 MHz

	Address	Type	Field Name	Default Value	Description
[Struct:16] HIF 0x201470	Host interface configurations. These values are primarily used for phExHif.
	0x201470	u8	bInterface	1 (hex)	Hif interfaces like I2C, SPI, HSU, USB or disabled. 0 : Disabled 1 : I2C 2 : SPI 3 : HSU 4 : USB
	0x201471	u8	bI2cConfig	0x00 (hex)	Refer phhalHif_Config_t->sI2cConfig in Hif module.
	0x201472	u8	bSpiConfig	0x00 (hex)	Refer phhalHif_Config_t->sSpiConfig in Hif module.
	0x201473	u8	bIsHsuBoot	0x00 (hex)	Set the Hsu Wakeup simulation.
	0x201474	u8	bEndOfFrame	0x00 (hex)	Hsu Eof size - Maximum interbyte duration.
	0x201475	u8	bStopBits	0x00 (hex)	Number of Hsu stop bits.
	0x201476	u8	bDummyBytes	0x00 (hex)	Number of Dummy bytes, used during standby phase.
	0x201477	u8	bBaudRate	0x00 (hex)	Refer phhalHif_Hsu_BaudRate_t.
	0x201478	u8	bBufferType	0 (hex)	Hif interfaces like I2C, SPI, HSU, USB or disabled. 0 : E_BUFFER_FORMAT_FREE, transparent (generic HW protocol format). 1 : E_BUFFER_FORMAT_FIXED, Header + Payload + Crc. 2 : E_BUFFER_FORMAT_NATIVE, transparent with Size at 1st Word.
	0x201479	u8	bShortFrameLen	0x00 (hex)	Number of bytes representing ShortFrame.
	0x20147a	u8	bStoreErrData	0x00 (hex)	Store error data or discard error data. 0 : Disabled 1 : Enabled
	0x20147b	u8	bHeaderSize	0x00 (hex)	Header Size in Fixed Format.
	0x20147c	u8	bTimeout	0x00 (hex)	Inter character Tx Timeout in steps of 3.6us.
	0x20147d	u8	bEnableVBUSPullDown	0x00 (hex)	If the user board takes more time than expected to detect discharge during self power mode, user can set this bit to discharge faster. There is a possibility of performance improvement of detecting USB disconnected based on PULLDOWN enabled/disabled.

Page V [phRFLP]

               Name : 65x65_PLM_MRA3              
            Antenna : 65x65 PLM              
      Last Modified : 2/1/2016              
        Last Author : Maniraj Ashirwad G              
     Version Number : Comments              
               V1.0 : Initial Version. Changes in this excel sheet and user_ee_65x65.xml &  should be logged further. User_ee.xml should be same as user_ee_65x65.xml while generating the eeprom for 65x65 Antenna.              
               V1.1 : DYNAMIC_BPSK_TH_ENABLE - Enabled for Felica Reader Mode Passive Initiator 212 and 424
    CLIF_ANA_CLK_MAN_REG - Register Value added for Felica Passive CM transition (For ALM :  GTM and Felica values are different)              
               V1.2 : All the test bus signal are disable except TX_ACTIVE on Digital Test Bus 1 (GPIO4) in user_ee_65x65_5V.xml
               V1.3 : For Type A RM 848   in CLIF_ANA_TX_SHAPE_CONTROL_REG register   TX_SET_TAU_MOD_FALLING   TX_SET_TAU_MOD_RISING are changed for RM A-848 fixing ISO OverShoot Failure
    For Type A RM 848 :  in CLIF_ANA_TX_AMPLITUDE_REG register   TX_GSN_MOD_RM is changed to fix ISO Overshoot Failure.
              V1.4  : Integration with the excel sheet PN5180_RF_ConfigurationSnapshot_20151103              
              V1.5  : 1. Bug Fix - SC3871
    2. Bit Fields of "CLIF_SIGPRO_ADCBCM_CONFIG_REG" :  are updated with MRA2 Bit Fields
             V1.5.1 : 1. Bug Fix - Type B update for "CLIF_TX_SYMBOL1_DEF_REG"              
             V1.5.2 : Bug Fix - SC3897. TX_CW_AMP_REF2TVDD is set to '0' in the boot settings              
               V1.6 : Integration with the PN5180 Eeprom Configuration "PN5180 FW RC4 release - V0.143". 
                    : Register Changes:
                    : CLIF_ANA_RX_REG -  A212, A424,A848, B424, B848, 1800 - 18.88 SC424 2M, 1800 - 18.88 SC424 4M, 1800 - 18.88 SC848 2M,1800 - 18.88 SC848 4M, 1800 - 9.44 SC424 2M, 1800 - 9.44 SC424 4M, 1800 - 9.44 SC848 2M, 1800 - 9.44 SC848 4M
                    : 
                    : CLIF_SIGPRO_RM_CONFIG1_REG - A212, A424, A848, B212, B424, B848,1800 - 18.88 SC424 2M, 1800 - 18.88 SC424 4M, 1800 - 9.44 SC424 2M, 1800 - 9.44 SC424 4M              
               V1.7 : No update - Created by Purnank              
             V1.7.1 : TXOCP configuration update for 65x65 <4v. Agc Ref = 220              
             V1.7.2 : CLIF_SIGPRO_ADCBCM_CONFIG_REG configuration update based for MRA2 Addition bit fields.
    CLIF_SIGPRO_ADCBCM_CONFIG_REG - GTM : CM - A106   A212   A424   A848   F212   F424   AI 212   AI 424
             V1.7.3 : PCD Shaping configuration update for 65x65              
             V1.7.4 : Renaming of TxOCP to DPC (eeprom xml files)              
               V1.8 : Separate PCD configuration added for <4v and >4v configuration              
             V1.8.1 : CLIF_ANA_NFCLD_REG value is updated - Initiator. 
    EDGE_DETECT_TAP_SEL updated for Type A 424 :  848 CM - Target              
             V1.8.2 : CLIF_ANA_NFCLD_REG set to 0x0C              
             V1.8.3 : CLIF_ANA_NFCLD_REG set to 0x07              
               V1.9 : 1. CLIF_TEST_CONTROL_REG added to the Initiator Tab
             V1.9.1 : Change for 30x50mm 5V DPC Config (AGC Hi Threshold) no change for 65x65mm              
             V1.9.2 : CLIF_ANA_NFCLD_REG set to 0x1C in boot setting              

Starting Address : 0x201480

	Address	Type	Field Name	Default Value	Description
[Struct:1] T_Tx_val 0x201480	Value to be applied to the corresponding CLIF register for CLIF Target Mode - Transmit.
	0x201480	u32	u32_T_TX_GTM_00_TRANSCEIVE_CONTROL_REG	7200 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: T_TX_GTM starts from here.
	0x201484	u32	u32_T_TX_GTM_01_ANA_PBF_CONTROL_REG	2c (hex)	Value for Register CLIF_ANA_PBF_CONTROL_REG.
	0x201488	u32	u32_T_TX_GTM_02_ANA_TX_AMPLITUDE_REG	ffff4000 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG.
	0x20148c	u32	u32_T_TX_GTM_03_ANA_TX_CLK_CONTROL_REG	1 (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
	0x201490	u32	u32_T_TX_GTM_04_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x201494	u32	u32_T_TX_GTM_05_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x201498	u32	u32_T_TX_GTM_06_ANA_TX_SHAPE_CONTROL_REG	0 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
	0x20149c	u32	u32_T_TX_GTM_07_TX_CONTROL_REG	0 (hex)	Value for Register CLIF_TX_CONTROL_REG.
	0x2014a0	u32	u32_T_TX_GTM_08_ANA_CLK_MAN_REG	10 (hex)	Value for Register CLIF_ANA_CLK_MAN_REG.
	0x2014a4	u32	u32_T_TX_A_106_P_00_TRANSCEIVE_CONTROL_REG	7202 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: T_TX_A_106_P starts from here.
	0x2014a8	u32	u32_T_TX_A_106_P_01_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x2014ac	u32	u32_T_TX_A_106_P_02_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x2014b0	u32	u32_T_TX_A_212_00_TRANSCEIVE_CONTROL_REG	7202 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: T_TX_A_212 starts from here.
	0x2014b4	u32	u32_T_TX_A_212_01_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x2014b8	u32	u32_T_TX_A_212_02_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x2014bc	u32	u32_T_TX_A_424_00_TRANSCEIVE_CONTROL_REG	7202 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: T_TX_A_424 starts from here.
	0x2014c0	u32	u32_T_TX_A_424_01_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x2014c4	u32	u32_T_TX_A_424_02_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x2014c8	u32	u32_T_TX_A_848_00_TRANSCEIVE_CONTROL_REG	7202 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: T_TX_A_848 starts from here.
	0x2014cc	u32	u32_T_TX_A_848_01_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x2014d0	u32	u32_T_TX_A_848_02_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x2014d4	u32	u32_T_TX_F_P_00_TRANSCEIVE_CONTROL_REG	0 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: T_TX_F_P starts from here.
	0x2014d8	u32	u32_T_TX_F_P_01_ANA_TX_AMPLITUDE_REG	ffff4000 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG.
	0x2014dc	u32	u32_T_TX_F_P_02_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x2014e0	u32	u32_T_TX_F_P_03_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x2014e4	u32	u32_T_TX_F_P_04_ANA_CLK_MAN_REG	10 (hex)	Value for Register CLIF_ANA_CLK_MAN_REG.
	0x2014e8	u32	u32_T_TX_ACT_00_ANA_PBF_CONTROL_REG	a0 (hex)	Value for Register CLIF_ANA_PBF_CONTROL_REG. Note: Configuration: T_TX_ACT starts from here.
	0x2014ec	u32	u32_T_TX_ACT_01_TX_CONTROL_REG	0 (hex)	Value for Register CLIF_TX_CONTROL_REG.
	0x2014f0	u32	u32_T_TX_ACT_02_ANA_CLK_MAN_REG	10 (hex)	Value for Register CLIF_ANA_CLK_MAN_REG.
	0x2014f4	u32	u32_T_TX_A_106_ACT_00_TRANSCEIVE_CONTROL_REG	35002 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: T_TX_A_106_ACT starts from here.
	0x2014f8	u32	u32_T_TX_A_106_ACT_01_ANA_TX_AMPLITUDE_REG	ffff50f4 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG.
	0x2014fc	u32	u32_T_TX_A_106_ACT_02_ANA_TX_CLK_CONTROL_REG	783 (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
	0x201500	u32	u32_T_TX_A_106_ACT_03_TX_UNDERSHOOT_CONFIG_REG	17 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x201504	u32	u32_T_TX_A_106_ACT_04_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x201508	u32	u32_T_TX_A_106_ACT_05_ANA_TX_SHAPE_CONTROL_REG	1b000f43 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
	0x20150c	u32	u32_T_TX_A_106_ACT_06_TX_DATA_MOD_REG	230104 (hex)	Value for Register CLIF_TX_DATA_MOD_REG.
	0x201510	u32	u32_T_TX_A_106_ACT_07_TX_SYMBOL23_MOD_REG	260104 (hex)	Value for Register CLIF_TX_SYMBOL23_MOD_REG.
	0x201514	u32	u32_T_TX_A_106_ACT_08_TX_SYMBOL01_MOD_REG	230104 (hex)	Value for Register CLIF_TX_SYMBOL01_MOD_REG.
	0x201518	u32	u32_T_TX_F_212_ACT_00_TRANSCEIVE_CONTROL_REG	30000 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: T_TX_F_212_ACT starts from here.
	0x20151c	u32	u32_T_TX_F_212_ACT_01_ANA_TX_AMPLITUDE_REG	ffff507c (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG.
	0x201520	u32	u32_T_TX_F_212_ACT_02_ANA_TX_CLK_CONTROL_REG	8f (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
	0x201524	u32	u32_T_TX_F_212_ACT_03_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x201528	u32	u32_T_TX_F_212_ACT_04_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x20152c	u32	u32_T_TX_F_212_ACT_05_ANA_TX_SHAPE_CONTROL_REG	7010744 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
	0x201530	u32	u32_T_TX_F_212_ACT_06_TX_DATA_MOD_REG	15 (hex)	Value for Register CLIF_TX_DATA_MOD_REG.
	0x201534	u32	u32_T_TX_F_212_ACT_07_TX_SYMBOL01_MOD_REG	15 (hex)	Value for Register CLIF_TX_SYMBOL01_MOD_REG.
	0x201538	u32	u32_T_TX_F_424_ACT_00_TRANSCEIVE_CONTROL_REG	30000 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: T_TX_F_424_ACT starts from here.
	0x20153c	u32	u32_T_TX_F_424_ACT_01_ANA_TX_AMPLITUDE_REG	ffff507c (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG.
	0x201540	u32	u32_T_TX_F_424_ACT_02_ANA_TX_CLK_CONTROL_REG	8f (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
	0x201544	u32	u32_T_TX_F_424_ACT_03_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x201548	u32	u32_T_TX_F_424_ACT_04_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x20154c	u32	u32_T_TX_F_424_ACT_05_ANA_TX_SHAPE_CONTROL_REG	7010f33 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
	0x201550	u32	u32_T_TX_F_424_ACT_06_TX_DATA_MOD_REG	16 (hex)	Value for Register CLIF_TX_DATA_MOD_REG.
	0x201554	u32	u32_T_TX_F_424_ACT_07_TX_SYMBOL01_MOD_REG	16 (hex)	Value for Register CLIF_TX_SYMBOL01_MOD_REG.
	0x201558	u32	u32_T_TX_B_00_ANA_TX_AMPLITUDE_REG	ffff0000 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: T_TX_B starts from here.

	Address	Type	Field Name	Default Value	Description
[Struct:2] T_Rx_val 0x20155c	Value to be applied to the corresponding CLIF register for CLIF Target Mode - Receive.
	0x20155c	u32	u32_T_RX_GTM_00_ANA_RX_REG	390a3 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: T_RX_GTM starts from here.
	0x201560	u32	u32_T_RX_GTM_01_ANA_AGC_REG	2 (hex)	Value for Register CLIF_ANA_AGC_REG.
	0x201564	u32	u32_T_RX_GTM_02_AGC_CONFIG1_REG	10207ff7 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
	0x201568	u32	u32_T_RX_GTM_03_AGC_CONFIG0_REG	4003 (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x20156c	u32	u32_T_RX_GTM_04_AGC_INPUT_REG	3000150 (hex)	Value for Register CLIF_AGC_INPUT_REG.
	0x201570	u32	u32_T_RX_GTM_05_SIGPRO_ADCBCM_THRESHOLD_REG	80060 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG.
	0x201574	u32	u32_T_RX_GTM_06_SIGPRO_ADCBCM_CONFIG_REG	f809d0d (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.
	0x201578	u32	u32_T_RX_GTM_07_ANA_CM_CONFIG_REG	4080 (hex)	Value for Register CLIF_ANA_CM_CONFIG_REG.
	0x20157c	u32	u32_T_RX_GTM_08_SIGPRO_CM_CONFIG_REG	6b40 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG.
	0x201580	u32	u32_T_RX_GTM_09_SIGPRO_RM_CONFIG1_REG	10ccc05 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x201584	u32	u32_T_RX_GTM_10_BBA_CONTROL_REG	0 (hex)	Value for Register CLIF_BBA_CONTROL_REG.
	0x201588	u32	u32_T_RX_A_00_SIGPRO_RM_CONFIG1_REG	0 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG. Note: Configuration: T_RX_A starts from here.
	0x20158c	u32	u32_T_RX_A_106_00_ANA_RX_REG	390a3 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: T_RX_A_106 starts from here.
	0x201590	u32	u32_T_RX_A_106_01_AGC_CONFIG1_REG	10207ff7 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
	0x201594	u32	u32_T_RX_A_106_02_AGC_CONFIG0_REG	44003 (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x201598	u32	u32_T_RX_A_106_03_SIGPRO_ADCBCM_THRESHOLD_REG	4003c (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG.
	0x20159c	u32	u32_T_RX_A_106_04_SIGPRO_ADCBCM_CONFIG_REG	180f9ed (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.
	0x2015a0	u32	u32_T_RX_A_106_05_ANA_CM_CONFIG_REG	4080 (hex)	Value for Register CLIF_ANA_CM_CONFIG_REG.
	0x2015a4	u32	u32_T_RX_A_106_06_SIGPRO_CM_CONFIG_REG	944 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG.
	0x2015a8	u32	u32_T_RX_A_106_07_BBA_CONTROL_REG	0 (hex)	Value for Register CLIF_BBA_CONTROL_REG.
	0x2015ac	u32	u32_T_RX_A_212_00_ANA_RX_REG	390a3 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: T_RX_A_212 starts from here.
	0x2015b0	u32	u32_T_RX_A_212_01_AGC_CONFIG1_REG	10207ff7 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
	0x2015b4	u32	u32_T_RX_A_212_02_AGC_CONFIG0_REG	44003 (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x2015b8	u32	u32_T_RX_A_212_03_SIGPRO_ADCBCM_THRESHOLD_REG	3000e0 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG.
	0x2015bc	u32	u32_T_RX_A_212_04_SIGPRO_ADCBCM_CONFIG_REG	880f9ef (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.
	0x2015c0	u32	u32_T_RX_A_212_05_ANA_CM_CONFIG_REG	7080 (hex)	Value for Register CLIF_ANA_CM_CONFIG_REG.
	0x2015c4	u32	u32_T_RX_A_212_06_SIGPRO_CM_CONFIG_REG	944 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG.
	0x2015c8	u32	u32_T_RX_A_212_07_BBA_CONTROL_REG	0 (hex)	Value for Register CLIF_BBA_CONTROL_REG.
	0x2015cc	u32	u32_T_RX_A_424_00_ANA_RX_REG	390a3 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: T_RX_A_424 starts from here.
	0x2015d0	u32	u32_T_RX_A_424_01_AGC_CONFIG1_REG	10207ff7 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
	0x2015d4	u32	u32_T_RX_A_424_02_AGC_CONFIG0_REG	44003 (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x2015d8	u32	u32_T_RX_A_424_03_SIGPRO_ADCBCM_THRESHOLD_REG	200040 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG.
	0x2015dc	u32	u32_T_RX_A_424_04_SIGPRO_ADCBCM_CONFIG_REG	8805d0f (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.
	0x2015e0	u32	u32_T_RX_A_424_05_ANA_CM_CONFIG_REG	4080 (hex)	Value for Register CLIF_ANA_CM_CONFIG_REG.
	0x2015e4	u32	u32_T_RX_A_424_06_SIGPRO_CM_CONFIG_REG	1144 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG.
	0x2015e8	u32	u32_T_RX_A_424_07_BBA_CONTROL_REG	0 (hex)	Value for Register CLIF_BBA_CONTROL_REG.
	0x2015ec	u32	u32_T_RX_A_848_00_ANA_RX_REG	390af (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: T_RX_A_848 starts from here.
	0x2015f0	u32	u32_T_RX_A_848_01_AGC_CONFIG1_REG	10207ff7 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
	0x2015f4	u32	u32_T_RX_A_848_02_AGC_CONFIG0_REG	44003 (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x2015f8	u32	u32_T_RX_A_848_03_SIGPRO_ADCBCM_THRESHOLD_REG	180040 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG.
	0x2015fc	u32	u32_T_RX_A_848_04_SIGPRO_ADCBCM_CONFIG_REG	41101e71 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.
	0x201600	u32	u32_T_RX_A_848_05_ANA_CM_CONFIG_REG	4080 (hex)	Value for Register CLIF_ANA_CM_CONFIG_REG.
	0x201604	u32	u32_T_RX_A_848_06_SIGPRO_CM_CONFIG_REG	1144 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG.
	0x201608	u32	u32_T_RX_A_848_07_BBA_CONTROL_REG	0 (hex)	Value for Register CLIF_BBA_CONTROL_REG.
	0x20160c	u32	u32_T_RX_F_00_ANA_RX_REG	390a3 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: T_RX_F starts from here.
	0x201610	u32	u32_T_RX_F_01_AGC_CONFIG1_REG	207ff6 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
	0x201614	u32	u32_T_RX_F_02_AGC_CONFIG0_REG	4400b (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x201618	u32	u32_T_RX_F_03_SIGPRO_ADCBCM_THRESHOLD_REG	80060 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG.
	0x20161c	u32	u32_T_RX_F_04_BBA_CONTROL_REG	0 (hex)	Value for Register CLIF_BBA_CONTROL_REG.
	0x201620	u32	u32_T_RX_F_212_00_SIGPRO_ADCBCM_CONFIG_REG	f80ad05 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG. Note: Configuration: T_RX_F_212 starts from here.
	0x201624	u32	u32_T_RX_F_212_01_SIGPRO_CM_CONFIG_REG	6206 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG.
	0x201628	u32	u32_T_RX_F_424_00_SIGPRO_ADCBCM_CONFIG_REG	f80ad09 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG. Note: Configuration: T_RX_F_424 starts from here.
	0x20162c	u32	u32_T_RX_F_424_01_SIGPRO_CM_CONFIG_REG	6206 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG.
	0x201630	u32	u32_T_RX_ACT_00_AGC_CONFIG1_REG	207ff6 (hex)	Value for Register CLIF_AGC_CONFIG1_REG. Note: Configuration: T_RX_ACT starts from here.
	0x201634	u32	u32_T_RX_ACT_01_AGC_CONFIG0_REG	4400b (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x201638	u32	u32_T_RX_A_106_ACT_00_SIGPRO_CM_CONFIG_REG	104 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG. Note: Configuration: T_RX_A_106_ACT starts from here.
	0x20163c	u32	u32_T_RX_F_212_ACT_00_SIGPRO_ADCBCM_THRESHOLD_REG	80060 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG. Note: Configuration: T_RX_F_212_ACT starts from here.
	0x201640	u32	u32_T_RX_F_212_ACT_01_SIGPRO_ADCBCM_CONFIG_REG	f801c85 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.
	0x201644	u32	u32_T_RX_F_212_ACT_02_SIGPRO_CM_CONFIG_REG	6206 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG.
	0x201648	u32	u32_T_RX_F_424_ACT_00_SIGPRO_ADCBCM_THRESHOLD_REG	80060 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG. Note: Configuration: T_RX_F_424_ACT starts from here.
	0x20164c	u32	u32_T_RX_F_424_ACT_01_SIGPRO_ADCBCM_CONFIG_REG	f801c89 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.
	0x201650	u32	u32_T_RX_F_424_ACT_02_SIGPRO_CM_CONFIG_REG	6206 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG.
	0x201654	u32	u32_T_RX_B_00_ANA_RX_REG	390a3 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: T_RX_B starts from here.
0x201658	u32	u32_T_RX_B_01_BBA_CONTROL_REG	341 (hex)	Value for Register CLIF_BBA_CONTROL_REG.
0x20165c	u32	u32_T_RX_B_106_00_SIGPRO_ADCBCM_THRESHOLD_REG	6400c8 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG. Note: Configuration: T_RX_B_106 starts from here.
0x201660	u32	u32_T_RX_B_106_01_SIGPRO_ADCBCM_CONFIG_REG	1780adef (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.
0x201664	u32	u32_T_RX_B_212_00_SIGPRO_ADCBCM_THRESHOLD_REG	6400c8 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG. Note: Configuration: T_RX_B_212 starts from here.
0x201668	u32	u32_T_RX_B_212_01_SIGPRO_ADCBCM_CONFIG_REG	17805def (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.
0x20166c	u32	u32_T_RX_B_424_00_SIGPRO_ADCBCM_THRESHOLD_REG	6400c8 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG. Note: Configuration: T_RX_B_424 starts from here.
0x201670	u32	u32_T_RX_B_424_01_SIGPRO_ADCBCM_CONFIG_REG	17805def (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.
0x201674	u32	u32_T_RX_B_848_00_SIGPRO_ADCBCM_THRESHOLD_REG	6400a8 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG. Note: Configuration: T_RX_B_848 starts from here.
0x201678	u32	u32_T_RX_B_848_01_SIGPRO_ADCBCM_CONFIG_REG	17805c71 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.

	Address	Type	Field Name	Default Value	Description
[Struct:3] I_Tx_val 0x20167c	Value to be applied to the corresponding CLIF register for CLIF Initiator Mode - Transmit.
	0x20167c	u32	u32_I_TX_00_ANA_PBF_CONTROL_REG	a0 (hex)	Value for Register CLIF_ANA_PBF_CONTROL_REG. Note: Configuration: I_TX starts from here.
	0x201680	u32	u32_I_TX_A_00_TRANSCEIVE_CONTROL_REG	5041 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: I_TX_A starts from here.
	0x201684	u32	u32_I_TX_A_106_00_ANA_TX_AMPLITUDE_REG	ffff50f4 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_A_106 starts from here.
	0x201688	u32	u32_I_TX_A_106_01_ANA_TX_CLK_CONTROL_REG	783 (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
	0x20168c	u32	u32_I_TX_A_106_02_TX_UNDERSHOOT_CONFIG_REG	17 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x201690	u32	u32_I_TX_A_106_03_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x201694	u32	u32_I_TX_A_106_04_ANA_TX_SHAPE_CONTROL_REG	1b000f43 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
	0x201698	u32	u32_I_TX_A_106_05_TX_DATA_MOD_REG	230104 (hex)	Value for Register CLIF_TX_DATA_MOD_REG.
	0x20169c	u32	u32_I_TX_A_106_06_TX_SYMBOL23_MOD_REG	230104 (hex)	Value for Register CLIF_TX_SYMBOL23_MOD_REG.
	0x2016a0	u32	u32_I_TX_A_106_07_TX_SYMBOL_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
	0x2016a4	u32	u32_I_TX_A_106_08_TX_SYMBOL01_MOD_REG	230104 (hex)	Value for Register CLIF_TX_SYMBOL01_MOD_REG.
	0x2016a8	u32	u32_I_TX_A_212_00_ANA_TX_AMPLITUDE_REG	ffff50f4 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_A_212 starts from here.
	0x2016ac	u32	u32_I_TX_A_212_01_ANA_TX_CLK_CONTROL_REG	83 (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
	0x2016b0	u32	u32_I_TX_A_212_02_TX_UNDERSHOOT_CONFIG_REG	5 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x2016b4	u32	u32_I_TX_A_212_03_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x2016b8	u32	u32_I_TX_A_212_04_ANA_TX_SHAPE_CONTROL_REG	1b000f43 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
	0x2016bc	u32	u32_I_TX_A_212_05_TX_DATA_MOD_REG	f0105 (hex)	Value for Register CLIF_TX_DATA_MOD_REG.
	0x2016c0	u32	u32_I_TX_A_212_06_TX_SYMBOL23_MOD_REG	f0105 (hex)	Value for Register CLIF_TX_SYMBOL23_MOD_REG.
	0x2016c4	u32	u32_I_TX_A_212_07_TX_SYMBOL_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
	0x2016c8	u32	u32_I_TX_A_424_00_ANA_TX_AMPLITUDE_REG	ffff50f4 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_A_424 starts from here.
	0x2016cc	u32	u32_I_TX_A_424_01_ANA_TX_CLK_CONTROL_REG	83 (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
	0x2016d0	u32	u32_I_TX_A_424_02_TX_UNDERSHOOT_CONFIG_REG	5 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x2016d4	u32	u32_I_TX_A_424_03_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x2016d8	u32	u32_I_TX_A_424_04_ANA_TX_SHAPE_CONTROL_REG	1b000f43 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
	0x2016dc	u32	u32_I_TX_A_424_05_TX_DATA_MOD_REG	60106 (hex)	Value for Register CLIF_TX_DATA_MOD_REG.
	0x2016e0	u32	u32_I_TX_A_424_06_TX_SYMBOL23_MOD_REG	60106 (hex)	Value for Register CLIF_TX_SYMBOL23_MOD_REG.
	0x2016e4	u32	u32_I_TX_A_424_07_TX_SYMBOL_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
	0x2016e8	u32	u32_I_TX_A_848_00_ANA_TX_AMPLITUDE_REG	ffff507c (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_A_848 starts from here.
	0x2016ec	u32	u32_I_TX_A_848_01_ANA_TX_CLK_CONTROL_REG	83 (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
	0x2016f0	u32	u32_I_TX_A_848_02_TX_UNDERSHOOT_CONFIG_REG	1 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x2016f4	u32	u32_I_TX_A_848_03_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x2016f8	u32	u32_I_TX_A_848_04_ANA_TX_SHAPE_CONTROL_REG	1f000f45 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
	0x2016fc	u32	u32_I_TX_A_848_05_TX_DATA_MOD_REG	10107 (hex)	Value for Register CLIF_TX_DATA_MOD_REG.
	0x201700	u32	u32_I_TX_A_848_06_TX_SYMBOL23_MOD_REG	10107 (hex)	Value for Register CLIF_TX_SYMBOL23_MOD_REG.
	0x201704	u32	u32_I_TX_A_848_07_TX_SYMBOL_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
	0x201708	u32	u32_I_TX_B_106_00_ANA_TX_AMPLITUDE_REG	ffff5094 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_B_106 starts from here.
	0x20170c	u32	u32_I_TX_B_106_01_ANA_TX_CLK_CONTROL_REG	8f (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
	0x201710	u32	u32_I_TX_B_106_02_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x201714	u32	u32_I_TX_B_106_03_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x201718	u32	u32_I_TX_B_106_04_ANA_TX_SHAPE_CONTROL_REG	7000756 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
	0x20171c	u32	u32_I_TX_B_106_05_TX_SYMBOL_CONFIG_REG	402b9 (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
	0x201720	u32	u32_I_TX_B_106_06_TX_SYMBOL01_MOD_REG	85 (hex)	Value for Register CLIF_TX_SYMBOL01_MOD_REG.
	0x201724	u32	u32_I_TX_B_106_07_TX_SYMBOL0_DEF_REG	1f (hex)	Value for Register CLIF_TX_SYMBOL0_DEF_REG.
	0x201728	u32	u32_I_TX_B_212_00_ANA_TX_AMPLITUDE_REG	ffff5074 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_B_212 starts from here.
	0x20172c	u32	u32_I_TX_B_212_01_ANA_TX_CLK_CONTROL_REG	8f (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
	0x201730	u32	u32_I_TX_B_212_02_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x201734	u32	u32_I_TX_B_212_03_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x201738	u32	u32_I_TX_B_212_04_ANA_TX_SHAPE_CONTROL_REG	7000746 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
	0x20173c	u32	u32_I_TX_B_212_05_TX_SYMBOL_CONFIG_REG	4014c (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
	0x201740	u32	u32_I_TX_B_212_06_TX_SYMBOL01_MOD_REG	85 (hex)	Value for Register CLIF_TX_SYMBOL01_MOD_REG.
	0x201744	u32	u32_I_TX_B_212_07_TX_SYMBOL0_DEF_REG	3 (hex)	Value for Register CLIF_TX_SYMBOL0_DEF_REG.
	0x201748	u32	u32_I_TX_B_424_00_ANA_TX_AMPLITUDE_REG	ffff5074 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_B_424 starts from here.
	0x20174c	u32	u32_I_TX_B_424_01_ANA_TX_CLK_CONTROL_REG	78f (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
	0x201750	u32	u32_I_TX_B_424_02_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x201754	u32	u32_I_TX_B_424_03_TX_OVERSHOOT_CONFIG_REG	1fe0013 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
	0x201758	u32	u32_I_TX_B_424_04_ANA_TX_SHAPE_CONTROL_REG	e000f54 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
	0x20175c	u32	u32_I_TX_B_424_05_TX_SYMBOL_CONFIG_REG	4014c (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
	0x201760	u32	u32_I_TX_B_424_06_TX_SYMBOL01_MOD_REG	86 (hex)	Value for Register CLIF_TX_SYMBOL01_MOD_REG.
	0x201764	u32	u32_I_TX_B_424_07_TX_SYMBOL0_DEF_REG	3 (hex)	Value for Register CLIF_TX_SYMBOL0_DEF_REG.
	0x201768	u32	u32_I_TX_B_848_00_ANA_TX_AMPLITUDE_REG	ffff506c (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_B_848 starts from here.
	0x20176c	u32	u32_I_TX_B_848_01_ANA_TX_CLK_CONTROL_REG	78f (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
	0x201770	u32	u32_I_TX_B_848_02_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
	0x201774	u32	u32_I_TX_B_848_03_TX_OVERSHOOT_CONFIG_REG	7e000d (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
0x201778	u32	u32_I_TX_B_848_04_ANA_TX_SHAPE_CONTROL_REG	d000f32 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
0x20177c	u32	u32_I_TX_B_848_05_TX_SYMBOL_CONFIG_REG	4014c (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
0x201780	u32	u32_I_TX_B_848_06_TX_SYMBOL01_MOD_REG	87 (hex)	Value for Register CLIF_TX_SYMBOL01_MOD_REG.
0x201784	u32	u32_I_TX_B_848_07_TX_SYMBOL0_DEF_REG	3 (hex)	Value for Register CLIF_TX_SYMBOL0_DEF_REG.
0x201788	u32	u32_I_TX_F_00_ANA_TX_CLK_CONTROL_REG	8f (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG. Note: Configuration: I_TX_F starts from here.
0x20178c	u32	u32_I_TX_F_212_00_ANA_TX_AMPLITUDE_REG	ffff507c (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_F_212 starts from here.
0x201790	u32	u32_I_TX_F_212_01_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
0x201794	u32	u32_I_TX_F_212_02_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
0x201798	u32	u32_I_TX_F_212_03_ANA_TX_SHAPE_CONTROL_REG	7010744 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
0x20179c	u32	u32_I_TX_F_424_00_ANA_TX_AMPLITUDE_REG	ffff507c (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_F_424 starts from here.
0x2017a0	u32	u32_I_TX_F_424_01_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
0x2017a4	u32	u32_I_TX_F_424_02_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
0x2017a8	u32	u32_I_TX_F_424_03_ANA_TX_SHAPE_CONTROL_REG	7010f33 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
0x2017ac	u32	u32_I_TX_15693_100_00_ANA_TX_AMPLITUDE_REG	ffff50f4 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_15693_100 starts from here.
0x2017b0	u32	u32_I_TX_15693_100_01_ANA_TX_CLK_CONTROL_REG	783 (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
0x2017b4	u32	u32_I_TX_15693_100_02_TX_UNDERSHOOT_CONFIG_REG	f000001f (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
0x2017b8	u32	u32_I_TX_15693_100_03_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
0x2017bc	u32	u32_I_TX_15693_100_04_ANA_TX_SHAPE_CONTROL_REG	1b000745 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
0x2017c0	u32	u32_I_TX_15693_100_05_TX_DATA_MOD_REG	43 (hex)	Value for Register CLIF_TX_DATA_MOD_REG.
0x2017c4	u32	u32_I_TX_15693_100_06_TX_SYMBOL23_MOD_REG	4 (hex)	Value for Register CLIF_TX_SYMBOL23_MOD_REG.
0x2017c8	u32	u32_I_TX_15693_100_07_TX_SYMBOL_CONFIG_REG	7c00 (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
0x2017cc	u32	u32_I_TX_15693_10_00_ANA_TX_AMPLITUDE_REG	ffff5090 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_15693_10 starts from here.
0x2017d0	u32	u32_I_TX_15693_10_01_ANA_TX_CLK_CONTROL_REG	8f (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
0x2017d4	u32	u32_I_TX_15693_10_02_TX_UNDERSHOOT_CONFIG_REG	ff000f (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
0x2017d8	u32	u32_I_TX_15693_10_03_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
0x2017dc	u32	u32_I_TX_15693_10_04_ANA_TX_SHAPE_CONTROL_REG	7010f44 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
0x2017e0	u32	u32_I_TX_15693_10_05_TX_DATA_MOD_REG	43 (hex)	Value for Register CLIF_TX_DATA_MOD_REG.
0x2017e4	u32	u32_I_TX_15693_10_06_TX_SYMBOL23_MOD_REG	4 (hex)	Value for Register CLIF_TX_SYMBOL23_MOD_REG.
0x2017e8	u32	u32_I_TX_15693_10_07_TX_SYMBOL_CONFIG_REG	7c00 (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
0x2017ec	u32	u32_I_TX_EPCV2_TARI_9_44_00_ANA_TX_AMPLITUDE_REG	fffff094 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_EPCV2_TARI_9_44 starts from here.
0x2017f0	u32	u32_I_TX_EPCV2_TARI_9_44_01_ANA_TX_CLK_CONTROL_REG	8f (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
0x2017f4	u32	u32_I_TX_EPCV2_TARI_9_44_02_TX_UNDERSHOOT_CONFIG_REG	ff000f (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
0x2017f8	u32	u32_I_TX_EPCV2_TARI_9_44_03_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
0x2017fc	u32	u32_I_TX_EPCV2_TARI_9_44_04_ANA_TX_SHAPE_CONTROL_REG	7000734 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
0x201800	u32	u32_I_TX_EPCV2_TARI_9_44_05_TX_SYMBOL_CONFIG_REG	ed (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
0x201804	u32	u32_I_TX_EPCV2_TARI_9_44_06_TX_SYMBOL0_DEF_REG	2841 (hex)	Value for Register CLIF_TX_SYMBOL0_DEF_REG.
0x201808	u32	u32_I_TX_EPCV2_TARI_9_44_07_TX_SYMBOL1_DEF_REG	a1 (hex)	Value for Register CLIF_TX_SYMBOL1_DEF_REG.
0x20180c	u32	u32_I_TX_EPCV2_TARI_18_88_00_ANA_TX_AMPLITUDE_REG	fffff08c (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG. Note: Configuration: I_TX_EPCV2_TARI_18_88 starts from here.
0x201810	u32	u32_I_TX_EPCV2_TARI_18_88_01_ANA_TX_CLK_CONTROL_REG	8f (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
0x201814	u32	u32_I_TX_EPCV2_TARI_18_88_02_TX_UNDERSHOOT_CONFIG_REG	ff000f (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
0x201818	u32	u32_I_TX_EPCV2_TARI_18_88_03_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
0x20181c	u32	u32_I_TX_EPCV2_TARI_18_88_04_ANA_TX_SHAPE_CONTROL_REG	7000734 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
0x201820	u32	u32_I_TX_EPCV2_TARI_18_88_05_TX_SYMBOL_CONFIG_REG	ed (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
0x201824	u32	u32_I_TX_EPCV2_TARI_18_88_06_TX_SYMBOL0_DEF_REG	2841 (hex)	Value for Register CLIF_TX_SYMBOL0_DEF_REG.
0x201828	u32	u32_I_TX_EPCV2_TARI_18_88_07_TX_SYMBOL1_DEF_REG	a1 (hex)	Value for Register CLIF_TX_SYMBOL1_DEF_REG.
0x20182c	u32	u32_I_TX_ACT_00_ANA_PBF_CONTROL_REG	a0 (hex)	Value for Register CLIF_ANA_PBF_CONTROL_REG. Note: Configuration: I_TX_ACT starts from here.
0x201830	u32	u32_I_TX_ACT_106_00_TRANSCEIVE_CONTROL_REG	35003 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: I_TX_ACT_106 starts from here.
0x201834	u32	u32_I_TX_ACT_106_01_ANA_TX_AMPLITUDE_REG	ffff50f4 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG.
0x201838	u32	u32_I_TX_ACT_106_02_ANA_TX_CLK_CONTROL_REG	783 (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
0x20183c	u32	u32_I_TX_ACT_106_03_TX_UNDERSHOOT_CONFIG_REG	17 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
0x201840	u32	u32_I_TX_ACT_106_04_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
0x201844	u32	u32_I_TX_ACT_106_05_ANA_TX_SHAPE_CONTROL_REG	1b000f43 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
0x201848	u32	u32_I_TX_ACT_106_06_TX_DATA_MOD_REG	230104 (hex)	Value for Register CLIF_TX_DATA_MOD_REG.
0x20184c	u32	u32_I_TX_ACT_106_07_TX_SYMBOL23_MOD_REG	260104 (hex)	Value for Register CLIF_TX_SYMBOL23_MOD_REG.
0x201850	u32	u32_I_TX_ACT_106_08_TX_SYMBOL_CONFIG_REG	9 (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
0x201854	u32	u32_I_TX_ACT_106_09_TX_SYMBOL01_MOD_REG	230104 (hex)	Value for Register CLIF_TX_SYMBOL01_MOD_REG.
0x201858	u32	u32_I_TX_ACT_212_00_TRANSCEIVE_CONTROL_REG	30001 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: I_TX_ACT_212 starts from here.
0x20185c	u32	u32_I_TX_ACT_212_01_ANA_TX_AMPLITUDE_REG	ffff507c (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG.
0x201860	u32	u32_I_TX_ACT_212_02_ANA_TX_CLK_CONTROL_REG	8f (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
0x201864	u32	u32_I_TX_ACT_212_03_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
0x201868	u32	u32_I_TX_ACT_212_04_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
0x20186c	u32	u32_I_TX_ACT_212_05_ANA_TX_SHAPE_CONTROL_REG	7010f44 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
0x201870	u32	u32_I_TX_ACT_212_06_TX_DATA_MOD_REG	15 (hex)	Value for Register CLIF_TX_DATA_MOD_REG.
0x201874	u32	u32_I_TX_ACT_212_07_TX_SYMBOL_CONFIG_REG	31000f (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
0x201878	u32	u32_I_TX_ACT_212_08_TX_SYMBOL01_MOD_REG	15 (hex)	Value for Register CLIF_TX_SYMBOL01_MOD_REG.
0x20187c	u32	u32_I_TX_ACT_424_00_TRANSCEIVE_CONTROL_REG	30001 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: I_TX_ACT_424 starts from here.
0x201880	u32	u32_I_TX_ACT_424_01_ANA_TX_AMPLITUDE_REG	ffff507c (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG.
0x201884	u32	u32_I_TX_ACT_424_02_ANA_TX_CLK_CONTROL_REG	8f (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
0x201888	u32	u32_I_TX_ACT_424_03_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
0x20188c	u32	u32_I_TX_ACT_424_04_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
0x201890	u32	u32_I_TX_ACT_424_05_ANA_TX_SHAPE_CONTROL_REG	7010f33 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
0x201894	u32	u32_I_TX_ACT_424_06_TX_DATA_MOD_REG	16 (hex)	Value for Register CLIF_TX_DATA_MOD_REG.
0x201898	u32	u32_I_TX_ACT_424_07_TX_SYMBOL_CONFIG_REG	31000f (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
0x20189c	u32	u32_I_TX_ACT_424_08_TX_SYMBOL01_MOD_REG	16 (hex)	Value for Register CLIF_TX_SYMBOL01_MOD_REG.
0x2018a0	u32	u32_I_TX_BOOT_00_TRANSCEIVE_CONTROL_REG	0 (hex)	Value for Register CLIF_TRANSCEIVE_CONTROL_REG. Note: Configuration: I_TX_BOOT starts from here.
0x2018a4	u32	u32_I_TX_BOOT_01_ANA_PBF_CONTROL_REG	a0 (hex)	Value for Register CLIF_ANA_PBF_CONTROL_REG.
0x2018a8	u32	u32_I_TX_BOOT_02_ANA_TX_AMPLITUDE_REG	ffff0003 (hex)	Value for Register CLIF_ANA_TX_AMPLITUDE_REG.
0x2018ac	u32	u32_I_TX_BOOT_03_ANA_TX_CLK_CONTROL_REG	83 (hex)	Value for Register CLIF_ANA_TX_CLK_CONTROL_REG.
0x2018b0	u32	u32_I_TX_BOOT_04_TX_UNDERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_UNDERSHOOT_CONFIG_REG.
0x2018b4	u32	u32_I_TX_BOOT_05_TX_OVERSHOOT_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_OVERSHOOT_CONFIG_REG.
0x2018b8	u32	u32_I_TX_BOOT_06_ANA_TX_SHAPE_CONTROL_REG	0 (hex)	Value for Register CLIF_ANA_TX_SHAPE_CONTROL_REG.
0x2018bc	u32	u32_I_TX_BOOT_07_TX_DATA_MOD_REG	0 (hex)	Value for Register CLIF_TX_DATA_MOD_REG.
0x2018c0	u32	u32_I_TX_BOOT_08_TX_SYMBOL23_MOD_REG	0 (hex)	Value for Register CLIF_TX_SYMBOL23_MOD_REG.
0x2018c4	u32	u32_I_TX_BOOT_09_TX_SYMBOL_CONFIG_REG	0 (hex)	Value for Register CLIF_TX_SYMBOL_CONFIG_REG.
0x2018c8	u32	u32_I_TX_BOOT_10_ANA_CLK_MAN_REG	0 (hex)	Value for Register CLIF_ANA_CLK_MAN_REG.
0x2018cc	u32	u32_I_TX_BOOT_11_TX_SYMBOL01_MOD_REG	0 (hex)	Value for Register CLIF_TX_SYMBOL01_MOD_REG.
0x2018d0	u32	u32_I_TX_BOOT_12_TX_SYMBOL0_DEF_REG	0 (hex)	Value for Register CLIF_TX_SYMBOL0_DEF_REG.
0x2018d4	u32	u32_I_TX_BOOT_13_TX_SYMBOL1_DEF_REG	0 (hex)	Value for Register CLIF_TX_SYMBOL1_DEF_REG.
0x2018d8	u32	u32_I_TX_BOOT_14_TEST_CONTROL_REG	280000 (hex)	Value for Register CLIF_TEST_CONTROL_REG.

	Address	Type	Field Name	Default Value	Description
[Struct:4] I_Rx_val 0x2018dc	Value to be applied to the corresponding CLIF register for CLIF Initiator Mode - Receive.
	0x2018dc	u32	u32_I_RX_PASS_00_ANA_AGC_REG	2 (hex)	Value for Register CLIF_ANA_AGC_REG. Note: Configuration: I_RX_PASS starts from here.
	0x2018e0	u32	u32_I_RX_PASS_01_AGC_INPUT_REG	20001f0 (hex)	Value for Register CLIF_AGC_INPUT_REG.
	0x2018e4	u32	u32_I_RX_A_106_P_00_ANA_RX_REG	2002f (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_A_106_P starts from here.
	0x2018e8	u32	u32_I_RX_A_106_P_01_SIGPRO_RM_CONFIG1_REG	440dc (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x2018ec	u32	u32_I_RX_A_106_P_02_AGC_CONFIG1_REG	3e40104 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
	0x2018f0	u32	u32_I_RX_A_106_P_03_AGC_CONFIG0_REG	7001008b (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x2018f4	u32	u32_I_RX_A_106_P_04_RX_CONFIG_REG	3 (hex)	Value for Register CLIF_RX_CONFIG_REG.
	0x2018f8	u32	u32_I_RX_A_212_00_ANA_RX_REG	20026 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_A_212 starts from here.
	0x2018fc	u32	u32_I_RX_A_212_01_SIGPRO_RM_CONFIG1_REG	1192605 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x201900	u32	u32_I_RX_A_212_02_AGC_CONFIG1_REG	3e10a04 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
	0x201904	u32	u32_I_RX_A_212_03_AGC_CONFIG0_REG	40c0b (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x201908	u32	u32_I_RX_A_212_04_RX_CONFIG_REG	23 (hex)	Value for Register CLIF_RX_CONFIG_REG.
	0x20190c	u32	u32_I_RX_A_424_00_ANA_RX_REG	20026 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_A_424 starts from here.
	0x201910	u32	u32_I_RX_A_424_01_SIGPRO_RM_CONFIG1_REG	1192905 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x201914	u32	u32_I_RX_A_424_02_AGC_CONFIG1_REG	3e10a04 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
	0x201918	u32	u32_I_RX_A_424_03_AGC_CONFIG0_REG	40c0b (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x20191c	u32	u32_I_RX_A_424_04_RX_CONFIG_REG	23 (hex)	Value for Register CLIF_RX_CONFIG_REG.
	0x201920	u32	u32_I_RX_A_848_00_ANA_RX_REG	20021 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_A_848 starts from here.
	0x201924	u32	u32_I_RX_A_848_01_SIGPRO_RM_CONFIG1_REG	10f2505 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x201928	u32	u32_I_RX_A_848_02_AGC_CONFIG1_REG	3e10a04 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
	0x20192c	u32	u32_I_RX_A_848_03_AGC_CONFIG0_REG	40c0b (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x201930	u32	u32_I_RX_A_848_04_RX_CONFIG_REG	23 (hex)	Value for Register CLIF_RX_CONFIG_REG.
	0x201934	u32	u32_I_RX_B_00_AGC_CONFIG1_REG	3e10a04 (hex)	Value for Register CLIF_AGC_CONFIG1_REG. Note: Configuration: I_RX_B starts from here.
	0x201938	u32	u32_I_RX_B_01_AGC_CONFIG0_REG	40c0b (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x20193c	u32	u32_I_RX_B_02_RX_CONFIG_REG	54 (hex)	Value for Register CLIF_RX_CONFIG_REG.
	0x201940	u32	u32_I_RX_B_106_00_ANA_RX_REG	2002b (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_B_106 starts from here.
	0x201944	u32	u32_I_RX_B_106_01_SIGPRO_RM_CONFIG1_REG	11f4615 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x201948	u32	u32_I_RX_B_212_00_ANA_RX_REG	20026 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_B_212 starts from here.
	0x20194c	u32	u32_I_RX_B_212_01_SIGPRO_RM_CONFIG1_REG	1192805 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x201950	u32	u32_I_RX_B_424_00_ANA_RX_REG	20026 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_B_424 starts from here.
	0x201954	u32	u32_I_RX_B_424_01_SIGPRO_RM_CONFIG1_REG	1192a05 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x201958	u32	u32_I_RX_B_848_00_ANA_RX_REG	2002a (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_B_848 starts from here.
	0x20195c	u32	u32_I_RX_B_848_01_SIGPRO_RM_CONFIG1_REG	10f2505 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x201960	u32	u32_I_RX_F_P_00_AGC_CONFIG1_REG	3e10a04 (hex)	Value for Register CLIF_AGC_CONFIG1_REG. Note: Configuration: I_RX_F_P starts from here.
	0x201964	u32	u32_I_RX_F_P_01_AGC_CONFIG0_REG	40c0b (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x201968	u32	u32_I_RX_F_P_02_RX_CONFIG_REG	38 (hex)	Value for Register CLIF_RX_CONFIG_REG.
	0x20196c	u32	u32_I_RX_F_212_P_00_ANA_RX_REG	20021 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_F_212_P starts from here.
	0x201970	u32	u32_I_RX_F_212_P_01_SIGPRO_RM_CONFIG1_REG	10f2605 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x201974	u32	u32_I_RX_F_424_P_00_ANA_RX_REG	20025 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_F_424_P starts from here.
	0x201978	u32	u32_I_RX_F_424_P_01_SIGPRO_RM_CONFIG1_REG	10f2605 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x20197c	u32	u32_I_RX_15693_00_AGC_CONFIG1_REG	3e40104 (hex)	Value for Register CLIF_AGC_CONFIG1_REG. Note: Configuration: I_RX_15693 starts from here.
	0x201980	u32	u32_I_RX_15693_01_AGC_CONFIG0_REG	7000008b (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x201984	u32	u32_I_RX_15693_02_RX_CONFIG_REG	1d10 (hex)	Value for Register CLIF_RX_CONFIG_REG.
	0x201988	u32	u32_I_RX_15693_26_00_ANA_RX_REG	2002a (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_15693_26 starts from here.
	0x20198c	u32	u32_I_RX_15693_26_01_SIGPRO_RM_CONFIG1_REG	c4010 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x201990	u32	u32_I_RX_15693_53_00_ANA_RX_REG	2002a (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_15693_53 starts from here.
	0x201994	u32	u32_I_RX_15693_53_01_SIGPRO_RM_CONFIG1_REG	c4010 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x201998	u32	u32_I_RX_EPCV2_00_AGC_CONFIG1_REG	3e40a04 (hex)	Value for Register CLIF_AGC_CONFIG1_REG. Note: Configuration: I_RX_EPCV2 starts from here.
	0x20199c	u32	u32_I_RX_EPCV2_01_AGC_CONFIG0_REG	c0b (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
	0x2019a0	u32	u32_I_RX_EPCV2_SC424_2MP_00_ANA_RX_REG	2002e (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_EPCV2_SC424_2MP starts from here.
	0x2019a4	u32	u32_I_RX_EPCV2_SC424_2MP_01_SIGPRO_RM_CONFIG1_REG	c6014 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x2019a8	u32	u32_I_RX_EPCV2_SC424_4MP_00_ANA_RX_REG	2002a (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_EPCV2_SC424_4MP starts from here.
	0x2019ac	u32	u32_I_RX_EPCV2_SC424_4MP_01_SIGPRO_RM_CONFIG1_REG	c8014 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x2019b0	u32	u32_I_RX_EPCV2_SC848_2MP_00_ANA_RX_REG	2002f (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_EPCV2_SC848_2MP starts from here.
	0x2019b4	u32	u32_I_RX_EPCV2_SC848_2MP_01_SIGPRO_RM_CONFIG1_REG	c8094 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x2019b8	u32	u32_I_RX_EPCV2_SC848_4MP_00_ANA_RX_REG	20022 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_EPCV2_SC848_4MP starts from here.
	0x2019bc	u32	u32_I_RX_EPCV2_SC848_4MP_01_SIGPRO_RM_CONFIG1_REG	c7094 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x2019c0	u32	u32_I_RX_ACT_00_ANA_AGC_REG	2 (hex)	Value for Register CLIF_ANA_AGC_REG. Note: Configuration: I_RX_ACT starts from here.
	0x2019c4	u32	u32_I_RX_ACT_01_SIGPRO_RM_CONFIG1_REG	10ccc05 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
	0x2019c8	u32	u32_I_RX_ACT_02_AGC_INPUT_REG	3000150 (hex)	Value for Register CLIF_AGC_INPUT_REG.
	0x2019cc	u32	u32_I_RX_ACT_03_ANA_CM_CONFIG_REG	14080 (hex)	Value for Register CLIF_ANA_CM_CONFIG_REG.
	0x2019d0	u32	u32_I_RX_ACT_04_BBA_CONTROL_REG	0 (hex)	Value for Register CLIF_BBA_CONTROL_REG.
	0x2019d4	u32	u32_I_RX_ACT_05_ANA_CLK_MAN_REG	10 (hex)	Value for Register CLIF_ANA_CLK_MAN_REG.
0x2019d8	u32	u32_I_RX_ACT_106_00_ANA_RX_REG	390a3 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_ACT_106 starts from here.
0x2019dc	u32	u32_I_RX_ACT_106_01_AGC_CONFIG1_REG	207ff6 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
0x2019e0	u32	u32_I_RX_ACT_106_02_AGC_CONFIG0_REG	4400b (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
0x2019e4	u32	u32_I_RX_ACT_106_03_SIGPRO_CM_CONFIG_REG	104 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG.
0x2019e8	u32	u32_I_RX_ACT_106_04_RX_CONFIG_REG	113 (hex)	Value for Register CLIF_RX_CONFIG_REG.
0x2019ec	u32	u32_I_RX_ACT_212_00_ANA_RX_REG	390a3 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_ACT_212 starts from here.
0x2019f0	u32	u32_I_RX_ACT_212_01_AGC_CONFIG1_REG	207ff6 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
0x2019f4	u32	u32_I_RX_ACT_212_02_AGC_CONFIG0_REG	4400b (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
0x2019f8	u32	u32_I_RX_ACT_212_03_SIGPRO_CM_CONFIG_REG	6206 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG.
0x2019fc	u32	u32_I_RX_ACT_212_04_SIGPRO_ADCBCM_THRESHOLD_REG	80060 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG.
0x201a00	u32	u32_I_RX_ACT_212_05_SIGPRO_ADCBCM_CONFIG_REG	f805d05 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.
0x201a04	u32	u32_I_RX_ACT_212_06_RX_CONFIG_REG	38 (hex)	Value for Register CLIF_RX_CONFIG_REG.
0x201a08	u32	u32_I_RX_ACT_424_00_ANA_RX_REG	390a3 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_ACT_424 starts from here.
0x201a0c	u32	u32_I_RX_ACT_424_01_AGC_CONFIG1_REG	207ff6 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
0x201a10	u32	u32_I_RX_ACT_424_02_AGC_CONFIG0_REG	4400b (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
0x201a14	u32	u32_I_RX_ACT_424_03_SIGPRO_CM_CONFIG_REG	6206 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG.
0x201a18	u32	u32_I_RX_ACT_424_04_SIGPRO_ADCBCM_THRESHOLD_REG	80060 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG.
0x201a1c	u32	u32_I_RX_ACT_424_05_SIGPRO_ADCBCM_CONFIG_REG	f805d09 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.
0x201a20	u32	u32_I_RX_ACT_424_06_RX_CONFIG_REG	38 (hex)	Value for Register CLIF_RX_CONFIG_REG.
0x201a24	u32	u32_I_RX_BOOT_00_ANA_RX_REG	3db20 (hex)	Value for Register CLIF_ANA_RX_REG. Note: Configuration: I_RX_BOOT starts from here.
0x201a28	u32	u32_I_RX_BOOT_01_ANA_AGC_REG	2 (hex)	Value for Register CLIF_ANA_AGC_REG.
0x201a2c	u32	u32_I_RX_BOOT_02_SIGPRO_RM_CONFIG1_REG	c0000 (hex)	Value for Register CLIF_SIGPRO_RM_CONFIG1_REG.
0x201a30	u32	u32_I_RX_BOOT_03_AGC_CONFIG1_REG	10107ff7 (hex)	Value for Register CLIF_AGC_CONFIG1_REG.
0x201a34	u32	u32_I_RX_BOOT_04_AGC_CONFIG0_REG	4007 (hex)	Value for Register CLIF_AGC_CONFIG0_REG.
0x201a38	u32	u32_I_RX_BOOT_05_AGC_INPUT_REG	3000150 (hex)	Value for Register CLIF_AGC_INPUT_REG.
0x201a3c	u32	u32_I_RX_BOOT_06_ANA_CM_CONFIG_REG	c080 (hex)	Value for Register CLIF_ANA_CM_CONFIG_REG.
0x201a40	u32	u32_I_RX_BOOT_07_ANA_TEST_REG	50004a (hex)	Value for Register CLIF_ANA_TEST_REG.
0x201a44	u32	u32_I_RX_BOOT_08_ANA_NFCLD_REG	1c (hex)	Value for Register CLIF_ANA_NFCLD_REG.
0x201a48	u32	u32_I_RX_BOOT_09_SIGPRO_CM_CONFIG_REG	4 (hex)	Value for Register CLIF_SIGPRO_CM_CONFIG_REG.
0x201a4c	u32	u32_I_RX_BOOT_10_SIGPRO_ADCBCM_THRESHOLD_REG	0 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_THRESHOLD_REG.
0x201a50	u32	u32_I_RX_BOOT_11_SIGPRO_ADCBCM_CONFIG_REG	1000000 (hex)	Value for Register CLIF_SIGPRO_ADCBCM_CONFIG_REG.
0x201a54	u32	u32_I_RX_BOOT_12_RX_CONFIG_REG	2 (hex)	Value for Register CLIF_RX_CONFIG_REG.
0x201a58	u32	u32_I_RX_BOOT_13_BBA_CONTROL_REG	0 (hex)	Value for Register CLIF_BBA_CONTROL_REG.

Page VI [Trailer]

Starting Address : 0x201a80

	Address	Type	Field Name	Default Value	Description
[Struct:1] Last 0x201a80	Last structure on EEPROM. Starting from this address/region, there is nothing relevent for the example/reference implementation.
	0x201a80	u32	dummyByte	0x32363437 (hex)	Dummy Byte for the Structure